Abstract:

Next Generation Analog Mixed Signal Design System
Mr. Jim Solomon

80% of SoC design starts now contain analog and mixed signal (AMS) components. This increase in AMS importance, coupled with the short time-to-market dictated by today’s consumer electronics, is putting pressure on existing design tools and methodologies. Mr. Solomon is the founder of Cadence Design Systems and has driven the development of AMS design tools that are in use by most analog design teams. He will discuss the emerging challenges seen in today’s SoC designs, and share his viewpoint on the most important tools and flows needed for a next generation AMS design system.

Universal PCell Technology
Mr. Ed Petrus

Parameterized Cells (PCells) are the building blocks of analog and mixed signal design implementation. PyCell Studio is a next generation PCell technology that enables the creation of complex PCells that support conditional rules in 90nm and below processes. This talk will cover the recent advancement in technology to support advanced PCell authoring.

Advanced Device Level Placement Technology
Dr. Lindor Henrickson

Analog and mixed signal layout development and migration for integrated SoC’s has always presented many challenges; however, recently, given the dramatic increases in design-rule complexity and mask costs, these challenges have become extreme. This is additionally coupled with ever increasing market pressure on IP developers to improve design turnaround and migration time. In these scenarios, computational technology must come to the fore and be leveraged to develop agile, flexible, and reliable automated layout methodologies. In this presentation, we will examine some of the challenges in advanced automated custom device-level layout generation and explore various approaches and solutions to the problem.

Advanced Analog Routing Technology
Mr. Kevin Steptoe

The talk will describe an advanced approach to the automation of routing particularly appropriate for the layout of analog, mixed signal and custom digital designs. The paper contrasts gridded (switchbox) and gridless (shape based) routing approaches for this application. The theme is developed to highlight the requirements of a complete routing system in which the balance between user interactivity and push button automation is achieved and crucially, in which comprehensive (electrical and physical) hierarchical constraints drive the result, providing the communication between designer intent in the front end and implementation in the back end.

舉辦時間: 96年2月6日 13:30-16:00
舉辦地點: 工業技術研究院 中興院區 9 館010會議室
主辦單位: 台灣SoC推動聯盟 / 工研院系統晶片科技中心
議程主席: 工研院系統晶片科技中心 張志偉副主任

Speaker's Bio

相關說明:

參加費用： TSoCC會員 $300 元 ; 非會員 $500 元 ; 學界比照TSoCC會員價;工研院同仁免費

線上報名：即日起至96年2月5日止（名額有限，請儘速報名,以免向隅） 報名連結

繳費方式:
1. 支票或郵政匯票： 抬頭請開列「工業技術研究院」，並以掛號寄至「新竹縣竹東鎮中興路4段 195號 9 館 200室 工研院台灣SoC推動聯盟 劉庭文小姐收」
2. 繳費方式:
戶名: 財團法人工業技術研究院
付款行:工研院分行 銀行帳號: 156-005-00002-5
銀行地址 : 新竹縣竹東鎮中興路4段195號52館
土地銀行--銀行代號:005
工研院分行—分行代號:1563
(請將銀行匯款收據影本傳真至03-582-0420 劉庭文小姐 以利核帳)

相關地圖參考：
工研院 來院路線圖
工研院 院內地圖

活動備註:

1.如遇不可抗力之因素而必須取消研討會, 主辦單位保留活動延期變更之權利。
2.已報名參加者 若因故無法前來,可請相關人員代表出席 或於活動前三天不含舉辦當天,以電話或Email 或傳真方式告知主辦單位,謝謝您的配合。
3.講義資料除提供參加學員外,額外索取部份需另額購買。

聯絡窗口：
劉庭文專員 Tel: 03-591-7591, Email: celialiu@itri.org.tw
江筱萍專員Tel:03-591-5533,Email:dorischiang@itri.org.tw
台灣SoC推動聯盟